1. Field of the Invention
The present invention relates to a semiconductor storage device and a memory cell test method, in particular, a semiconductor storage device to which a plurality of memory test processes are performed under different conditions and a test method thereof.
2. Description of Related Art
Generally, in manufacturing a semiconductor storage device, primary memory cells and redundancy memory cells are manufactured. The redundancy memory cell serves as an auxiliary element when a primary memory cell does not operate. When the primary memory cell is not defective, they are used as a memory cell in the storage device. In a case that a primary memory cell is detected to be defective, the connection of the memory cell with the surrounding circuits is replaced with the connection of a redundancy memory cell with the same surrounding circuits, thereby the defective memory cell is salvaged.
The redundancy memory cell is provided in a device as a unit of a word line or a digit select line (bit line), for example. Such a semiconductor storage device has a memory section including a (primary) memory cell usually contributes to the storage capacity and redundancy memory cells for salvaging defective cells, defective word lines or defective digit select lines which may exist in the memory section. The redundancy memory cells include a redundancy row memory cell for a word line and a redundancy column memory cell for a digit select line and are arranged disposed near the memory section or in the memory section.
FIG. 1 is a block diagram showing a configuration of a semiconductor storage device according to a first reference example for explaining the present invention. The semiconductor storage device 300 according to the first reference example has a memory section 1, a redundancy row memory section 2, a redundancy column memory section 3, a redundancy row and column memory section 4, a row decoder group 311, a row predecoder group 312, a row redundancy circuit section 313, a row buffer circuit 314, a row redundancy decoder group 315, a column decoder group 321, a column predecoder group 322, a column redundancy circuit section 323, a column buffer circuit 324 and a column redundancy decoder group 325.
The memory section 1 has a plurality of memory cells C00 to Cnm which are provided in intersection regions between word lines X0 to Xn and digit select lines Y0 to Ym. The redundancy row memory section 2 has a plurality of redundancy row memory cells RXC00 to RXCpm which are provided in intersection regions between redundancy word lines RX0 to RXp and the digit select lines Y0 to Ym. The redundancy column memory section 3 has a plurality of redundancy column memory cells RYC00 to RYCnq which are provided in intersection regions between the word lines X0 to Xn and redundancy digit select lines RY0 to RYq. The redundancy row and column memory section 4 has a plurality of redundancy row and column memory cells RXYC00 to RXYCpq which are provided in intersection regions between the redundancy word lines RX0 to RXp and the redundancy digit select lines RY0 to RYq.
The row decoder group 311 is activated in accordance with a selection signal outputted from the row predecoder group 312, selects one of the word lines X0 to Xn and activates the selected word line. The column decoder group 321 is activated in accordance with a selection signal outputted from the column predecoder group 322 and selects one of the digit select lines Y0 to Ym. The row redundancy decoder group 315 is activated in accordance with a selection signal outputted from the row redundancy circuit section via the row buffer circuit 314 and selects one of the redundancy word lines RX0 to RXp. The column redundancy decoder group 325 is activated in accordance with a selection signal outputted from the column redundancy circuit section via the column buffer circuit 324 and selects one of the redundancy digit select lines RY0 to RYq.
The row redundancy circuit section 313 selects one of the row decoder group 311 and the row redundancy decoder group 315 as a decoder for selecting a word line based on a fuse circuit which is built therein and a row address signal 101. When the row decoder group 311 is selected and used, the row redundancy circuit section 313 outputs a signal for using the row decoder group 311 to the row predecoder group 312 as well as outputs a signal for inactivating the row redundancy decoder group 315 to the row buffer circuit 314. In this case, the row predecoder group 312 outputs a selection signal corresponding to the inputted row address signal 101. On the other hand, when the row redundancy decoder group 315 is selected and used, the row redundancy circuit section 313 outputs a selection signal to the row redundancy decoder group 315 as well as outputs a signal for inactivating the row predecoder group 312. In this case, the row redundancy decoder group 315 selects one of the redundancy word lines RX0 to RXp in accordance with a selection signal inputted via the row buffer circuit 314.
The row redundancy circuit section 313 has a plurality of row redundancy circuits shown in FIG. 2. Each row redundancy circuit includes an enable fuse circuit 30 and address fuse circuits F0 to F10, to which an INT signal 107 is inputted, an NMOS transistor 31 connected to the enable fuse circuit 30 at its gate, NMOS transistors Mn0 to Mn10 connected to the address fuse circuits F0 to F10, respectively, at their gates, PMOS transistors 32, 33 connected to a first power source VDD of a high-potential side at their sources and respectively connected to nodes N1, N2 at their drains, NMOS transistors 34, 35 connected to a second power source VSS of a low-potential side at their sources and connected to a node N5 at their gates, a NAND gate 37 for outputting NAND of input signals from the node N1 and the node N2 as a selection signal XREDB, and PMOS transistors 36 respectively connected to the node N1 and the node N2 at their drains and receive an input of the selection signal XREDB at their gates.
When a signal of an “L” level is inputted to at least either the node N1 or N2, the NAND gate 37 outputs the selection signal XREDB of the “H” level to the row redundancy decoder group 315. When a signal of the “H” level is inputted to both of the nodes N1 and N2, the NAND gate 37 outputs the selection signal XREDB of the “L” level to the row redundancy decoder group 315.
When both of the nodes N1, N2 are at the “H” level, it is determined that the selection signal XREDB is at the “L” level and the row redundancy memory cell is used. This state is referred to as an activated state of the row redundancy circuit. When one of the nodes N1, N2 is at the “L” level, it is determined that the selection signal XREDB is at the “H” level and the row redundancy memory cell is not used. This state is referred to as an inactivated state of the row redundancy circuit.
The signal level at the node N1 is determined by driving condition of the NMOS transistors 31 and Mn0 to Mn4. Furthermore, the signal level of the node N2 is determined by driving condition of the NMOS transistors Mn5 to 10. The driving condition of the NMOS transistor 31 is determined by connection/disconnection state of a fuse in the enable fuse circuit 30. The driving condition of each of the NMOS transistors Mn0 to Mn10 is determined by connection/disconnection state of the corresponding fuse in the address fuse circuits F0 to F10 and row address signals XA00 to XA10.
The column redundancy circuit section 323 selects either the column decoder group 321 or the column redundancy decoder group 325 as a decoder for selecting a digit select line on the basis of fuse circuits built therein and a column address signal 201. When the column decoder group 321 is selected and used, the column redundancy circuit section 323 outputs a signal for using the column decoder group 321 to the column predecoder group 322 as well as outputs a signal for inactivating the column redundancy decoder group 325 to the column buffer circuit 324. In this case, the column predecoder group 322 outputs a selection signal corresponding to the inputted column address signal 201 to the column decoder group 321. On the other hand, when the column redundancy decoder group 325 is selected and used, the column redundancy circuit section 323 outputs a selection signal to the column redundancy decoder group 325 as well as outputs a signal for inactivating the column predecoder group 322. In this case, the column redundancy decoder group 325 selects one of the redundancy digit select lines RY0 to RYq in accordance with a selection signal inputted via the column buffer circuit 324.
The column redundancy circuit section 323 has a plurality of column redundancy circuits having a similar configuration to the above-mentioned row redundancy circuits. Each column redundancy circuit outputs a selection signal corresponding to the connection/disconnection state of a built-in fuse and an input column address signal 201 to the column redundancy decoder group 325. An operation of the redundancy circuit will be described below referring to the row redundancy circuit.
In FIG. 2, when the ACT signal 106 is at the “L” level, the PMOS transistors 32, 33 change the nodes N1, N2 to the “H” level and the NMOS transistors 34, 35 keeps the nodes N3, N4 at the “H” level. During this time, the nodes N1 to N4 are precharged.
When the ACT signal becomes the “H” level, precharge of the nodes N1 to N4 is released and the NMOS transistors 34, 35 are changed to conducting state. Here, when the output of the enable fuse circuit 30 is the “H” level, the node N1 is at the “L” level irrespectively of combination of the address signals XA00 to XA10, and the row redundancy circuits become inactivated. When the output of the enable fuse circuit 30 is the “L” level, the level of each of the nodes N1, N2 is determined by combination of the address signals XA00 to XA10, thereby activation/inactivation of the row redundancy circuits is determined. When the outputs of the address fuse circuits F0 to F10 are all “L” level in accordance with combination of the address signals XA00 to XA10 for activating the row redundancy circuits, the nodes N1, N2 are kept at the “H” level. Thereby, the selection signal XREDB becomes the “L” level and a row redundancy word line (row redundancy memory cell) is selected.
The enable fuse circuit 30 is implemented by a FUSE circuit 60 shown in FIG. 3. The FUSE circuit 60 has a PMOS transistor 50, a fuse 51, NMOS transistors 52, 53 and inverters 54, 55. The PMOS transistor 50 and the NMOS transistor 52 form an inverter having INT signal 107 as an input and the node N7 as an output. The fuse 51 is connected between the drain of the PMOS transistor 50 and the node N7. The node 7 is connected to an output terminal OUT1 via the inverters 54, 55. The output terminal OUT1 of the enable fuse circuit 30 is connected to the gate of the NMOS transistor 31 shown in FIG. 2. The gate of the NMOS transistor 53 is connected to the output of the inverter 54 and the drain thereof is connected to the node N7. The NMOS transistor 53 fixes the output level of the inverter 54.
Here, the INT signal 107 is a one-shot pulse signal which is at the “H” level only at a period just after turned-on and then, becomes the “L” level. The INT signal 107 may be inputted from an outside signal or may be generated in the semiconductor storage device 300 shown in FIG. 1.
When the fuse 51 is fused, namely, the fuse 51 is blown to disconnect the electrical connection, the signal level at the output terminal OUT1 becomes “L” in accordance with the one-shot INT signal 107 of the “H” level. In this case, the NMOS transistor 31 is turned off and the signal level at the node N1 is determined by the NMOS transistors Mn0 to Mn4. On the other hand, when the fuse 51 is not fused, the PMOS transistor 50 and the NMOS transistor 52 operate as an inverter and the signal level of the output terminal OUT1 becomes the “H” in accordance with the INT signal 107 of the “L” level after the one-shot pulse. In this case, the signal level at the node N1 is lowered by the NMOS transistor 31 and becomes the “L” level. That is, in a trimming process, the fuse 51 is fused for setting the row redundancy circuit 130 to the activated state and is not fused for setting it to the inactivated state.
Referring to FIG. 2, the NMOS transistors Mn0 to Mn10 determine the signal level of each of the nodes N1 and N2 in accordance with the signal levels inputted from the address fuse circuits F0 to F10, respectively. The address fuse circuits F0 to F10 determine the signal levels inputted to gates of the NMOS transistors Mn0 to 10 in accordance with the signal levels of the INT signal 107 and the row address signals XA00 to XA10 and the connection/disconnection state of the FUSE circuit 60 built therein.
Each of the address fuse circuits F0 to F10 is implemented by the FUSE circuit 70 shown in FIG. 4. FIG. 4 is a circuit diagram showing a configuration of the address fuse circuit F0. Configurations of the address fuse circuits F1 to F10 are the same as that of the address fuse circuit F0. The FUSE circuit 70 has a FUSE circuit 60 connected between a terminal to which the INT signal 107 is inputted and the node N8, a transfer gate 62 which is controlled by a complementary signal from the node N8 and outputs a signal corresponding to the row address signal XA00 to the output terminal OUT2 (the gate of the NMOS transistor Mn0) and a transfer gate 63 which is controlled by a complementary signal from the node N8 and outputs a signal corresponding to an inversion signal of the row address signal XA00 to the output terminal OUT2. Here, the output terminal OUT1 of the FUSE circuit 60 is connected to the node N8. As described above, the INT signal 107 is outputted as a one-shot pulse signal of the “H” level only at turn-on period and then, becomes the “L” level.
When the fuse 51 of the FUSE circuit 60 provided in the FUSE circuit 70 is fused, the signal level of the output terminal OUT2 becomes a signal level obtained by inverting the row address signal XA00. On the other hand, when the fuse 51 is not is not fused, the signal level of the output terminal OUT2 becomes a same signal level as that of the row address signal XA00.
For example, for setting the row redundancy circuit to the activated state under the condition that the row address signal XA00 is at the “H” level, the fuse 51 of the address fuse circuit F0 is fused. In this case, in accordance with the row address signal XA00 of the “H” level, the gate of the NMOS transistor Mn0 becomes the “L” level and the node N1 transitions to the “H” level. Conversely, in accordance with the row address signal XA00 of the “L” level, the gate of the NMOS transistor Mn0 becomes the “H” level and the node N1 transitions to the “L” level.
On the other hand, for setting the row redundancy circuit to the activated state under the condition that the address signal XA00 is at the “L” level, the fuse 51 of the address fuse circuit F0 is not fused. Correspondence between combination of the signal levels of the address signals XA00 to XA10 for bringing a row redundancy circuit into the activated state and the connection/disconnection state of the fuse 51 can be appropriately set for each row redundancy circuit and each address fuse circuit.
Regardless of the connection/disconnection states of the address fuse circuits F0 to F10, it is possible to activate the row redundancy circuit 130 with some sort of address information. For refusing the use of the row redundancy circuit 130, since it is required to achieve the inactivated state independently of the address information, the enable fuse circuit 30 is required.
As described above, whether the row redundancy circuit is used or not is determined by the enable fuse circuit 30 and when the row redundancy circuit is used, activation/inactivation is determined depending on the address fuse circuits F0 to F10 and the row address signals XA00 to XA10. The selection signal XREDB outputted from the activated row redundancy circuit drives a row redundancy decoder and activates a redundancy word line.
In this reference example, after the semiconductor storage device 300 with the aforementioned configuration is formed on a wafer, a memory test is carried out. In a memory test, existence/absence of defects in the memory section 1 is detected. A defective cell, a defective word line or a defective digit select line which is detected in the memory test is salvaged by being replaced with the redundancy memory section (the redundancy row memory section 2, the redundancy column memory section 3 or the redundancy row and column memory section 4), which is called trimming process.
Describing the trimming process in detail, when a plurality of tests are carried out in a memory cell test process and a defect spot is detected, fuse information is generated to salvage a defect address corresponding the defect spot. Next, in the trimming process, based on the fuse information, fuse circuits of the row redundancy circuit section 313 and the column redundancy circuit section 323 are fused. At this time, the fuse circuits are fused so as to select a replaced redundancy memory cell in accordance with an address signal for selecting the defect spot in the memory section 1. For example, the fuse circuit in the row redundancy circuit section 313 is fused so as to select (to activate) any one of the redundancy word lines RX0 to RXp in place of the defect spot on the word lines X0 to Xn. The fuse circuit in the column redundancy circuit section 323 is fused so as to select (to activate) any one of the redundancy digit select lines RY0 to RYq in place of the defect spot on the digit select lines Y0 to Ym. Thereby, the memory cell corresponding to the defect address is replaced with the redundancy memory cell. As long as there is no defect in the redundancy memory cell which is used for replacing the defective memory cell by trimming, the semiconductor storage device becomes a non-defective product under the conditions of the memory test.